计数器：std_logic_unsigned的用法
-- This example shows the use of the package 'std_logic_unsigned' .
-- The minus operator '-' is overloaded by this package, thereby allowing an integer to be subracted from a std_logic_vector.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY pldcntr8 IS
PORT (clk, load : IN Std_logic;
datain : IN Std_logic_vector(7 DOWNTO 0);
q : OUT Std_logic_vector(7 DOWNTO 0);
tc : OUT Std_logic);
END pldcntr8;
ARCHITECTURE using_std_logic OF pldcntr8 IS
SIGNAL count : Std_logic_vector(7 DOWNTO 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge(clk);
IF load = '1' THEN
count <= datain;
ELSE
count <= count - 1;
END IF;
END PROCESS;
tc <= '1' WHEN count = "00000000" ELSE '0';
q <= count;
END using_std_logic;
条件赋值：使用when else语句
-- Conditional Signal Assignment
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsig IS
PORT
(
input0, input1, sel : IN BIT;
output : OUT BIT
);
END condsig;
ARCHITECTURE maxpld OF condsig IS
BEGIN
output <= input0 WHEN sel = '0' ELSE input1;
END maxpld;
加法器：generate语句的应用
-- n-bit Adder using the Generate Statement
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY addn IS
GENERIC(n : POSITIVE := 3); --no. of bits less one
PORT(addend, augend : IN BIT_VECTOR(0 TO n);
carry_in : IN BIT; carry_out, overflow : OUT BIT;
sum : OUT BIT_VECTOR(0 TO n));
END addn;
ARCHITECTURE generated OF addn IS
SIGNAL carries : BIT_VECTOR(0 TO n);
BEGIN
addgen : FOR i IN addend'RANGE
GENERATE
lsadder : IF i = 0 GENERATE
sum(i) <= addend(i) XOR augend(i) XOR carry_in;
carries(i) <= (addend(i) AND augend(i)) OR
(addend(i) AND carry_in) OR
(carry_in AND augend(i));
END GENERATE;
otheradder : IF i /= 0 GENERATE
sum(i) <= addend(i) XOR augend(i) XOR carries(i-1);
carries(i) <= (addend(i) AND augend(i)) OR
(addend(i) AND carries(i-1)) OR
(carries(i-1) AND augend(i));
END GENERATE;
END GENERATE;
carry_out <= carries(n);
overflow <= carries(n-1) XOR carries(n);
END generated;
条件赋值：使用列举类型
-- Selected Signal Assignment with Enumeration Type
Library IEEE ;
use IEEE.std_logic_1164.all ;
PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LUNCH, DINNER, MIDNIGHT_SNACK);
END meals_pkg;
USE work.meals_pkg.all;
ENTITY selsigen IS
PORT
(
previous_meal : IN MEAL;
next_meal : OUT MEAL
);
END selsigen;
ARCHITECTURE maxpld OF selsigen IS
BEGIN
WITH previous_meal SELECT
next_meal <= BREAKFAST WHEN DINNER | MIDNIGHT_SNACK,
LUNCH WHEN BREAKFAST,
DINNER WHEN LUNCH;
END maxpld;
计数器：generate语句的应用
-- Generated Binary Up Counter
-- The first design entity is a T-type flip-flop.
-- The second is an scalable synchronous binary up counter illustrating the use of the generate statement to produce regular structures of components.
library ieee;
use ieee.std_logic_1164.all;
entity tff is
port(clk, t, clear : in std_logic; q : buffer std_logic);
end tff;
architecture v1 of tff is
begin
process(clear, clk)
begin
if clear = '1' then
q <= '0';
elsif rising_edge(clk) then
if t = '1' then
q <= not q;
else
null;
end if;
end if;
end process;
end v1;
library ieee;
use ieee.std_logic_1164.all;
entity bigcntr is
generic(size : positive := 32);
port(clk, clear : in std_logic;
q : buffer std_logic_vector((size-1) downto 0));
end bigcntr;
architecture v1 of bigcntr is
component tff is
port(clk, t, clear : in std_logic; q : buffer std_logic);
end component;
signal tin : std_logic_vector((size-1) downto 0);
begin
genttf : for i in (size-1) downto 0 generate
ttype : tff port map (clk, tin(i), clear, q(i));
end generate;
genand : for i in 0 to (size-1) generate
t0 : if i = 0 generate
tin(i) <= '1';
end generate;
t1_size : if i > 0 generate
tin(i) <= q(i-1) and tin(i-1);
end generate;
end generate;
end v1;
条件赋值：使用多路选择器
-- Conditional Signal Assignment with Multiple Alternatives
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY condsigm IS
PORT
(
high, mid, low : IN BIT;
q : OUT INTEGER
);
END condsigm;
ARCHITECTURE maxpld OF condsigm IS
BEGIN
q <= 3 WHEN high = '1' ELSE -- when high
2 WHEN mid = '1' ELSE -- when mid but not high
1 WHEN low = '1' ELSE -- when low but not mid or high
0; -- when not low, mid, or high
END maxpld;
计数器：GENERIC语句的应用
-- n-Bit Synchronous Counter
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY cntrnbit IS
GENERIC(n : Positive := 8);
PORT(clock, reset, enable : IN Std_logic;
count : OUT Std_logic_vector((n-1) DOWNTO 0));
END cntrnbit;
ARCHITECTURE v1 OF cntrnbit IS
SIGNAL count_int : Std_logic_vector((n-1) DOWNTO 0);
BEGIN
PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
IF reset = '1' THEN
count_int <= (OTHERS => '0');
ELSIF enable = '1' THEN
count_int <= count_int + 1;
ELSE
NULL;
END IF;
END PROCESS;
count <= count_int;
END v1;
无符号数到整数的转换
-- Conversion Function
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY adder IS
PORT (op1, op2 : IN UNSIGNED(7 downto 0);
result : OUT INTEGER);
END adder;
ARCHITECTURE maxpld OF adder IS
BEGIN
result <= CONV_INTEGER(op1 + op2);
END maxpld;
计数器：wait语句的应用
-- This example shows an inefficient way of describing a counter.
-- vhdl model of a 3-state counter illustrating the use
-- of the WAIT statement to suspend a process.At each wait
-- statement the simulation time is updated one cycle,transferring
-- the driver value to the output count.
-- This architecture shows that there is no difference between
-- WAIT UNTIL (clock'EVENT AND clock = '1') and WAIT UNTIL clock = '1'
library ieee;
use ieee.std_logic_1164.all;
ENTITY cntr3 IS
PORT(clock : IN BIT; count : OUT NATURAL);
END cntr3;
ARCHITECTURE using_wait OF cntr3 IS
BEGIN
PROCESS
BEGIN
--WAIT UNTIL (clock'EVENT AND clock = '1');
WAIT UNTIL clock = '1';
count <= 0;
--WAIT UNTIL (clock'EVENT AND clock = '1');
WAIT UNTIL clock = '1';
count <= 1;
--WAIT UNTIL (clock'EVENT AND clock = '1');
WAIT UNTIL clock = '1';
count <= 2;
END PROCESS;
END using_wait;
元件例化与层次设计
VHDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using VHDL.
The top-level design, called top.vhd, implements an instance of the function logic.vhd.
In the top.vhd file, a component for the logic function is declared inside the architecture in which it is instantiated.
The Component Declaration defines the ports of the lower-level function.
-----------------------------------------------------------------------------
top.vhd (Top-level file)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top IS
PORT(w_in, x_in, y_in :IN std_logic;
clock :IN std_logic;
z_out :OUT std_logic);
END top;
ARCHITECTURE a OF top IS
COMPONENT logic
PORT(a,b,c :IN std_logic;
x :OUT std_logic);
END COMPONENT;
SIGNAL w_reg, x_reg, y_reg, z_reg :std_logic;
BEGIN
low_logic : logic PORT MAP (a => w_reg, b => x_reg, c => y_reg, x => z_reg);
PROCESS(clock)
BEGIN
IF (clock'event AND clock='1') THEN
w_reg<=w_in;
x_reg<=x_in;
y_reg<=y_in;
z_out<=z_reg;
END IF;
END PROCESS;
END a;
--------------------------------------------------------------------------------
logic.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY logic IS
PORT(a,b,c : IN std_logic;
x : OUT std_logic);
END logic;
ARCHITECTURE a OF logic IS
BEGIN
PROCESS (a,b,c)
BEGIN
x<=(a and b) or c;
END PROCESS;
END;
将16进制转化为std_logic
VHDL: Converting a Hexadecimal Value to a Standard Logic Vector
