VHDL 程序举例
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重要说明：不同软件对VHDL语法的支持范围是不一样的，以下程序中的某些语句可能不能运行在所有的软件平台之上，因此程序可能要作一些修改，同时务必注意阅读程序中的注释。以下部分程序为txt格式，请自行另存为vdh后缀的文件。有些EDA软件要求ENTITY的名称和文件名要相同，也请自行修改。 如发现错误请来信指正或在BBS上提出。
最高优先级编码器 :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity priority is
port(I : in bit_vector(7 downto 0); --inputs to be prioritised
A : out bit_vector(2 downto 0); --encoded output
GS : out bit); --group signal output
end priority;
architecture v1 of priority is
begin
process(I)
begin
GS <= '1'; --set default outputs
A <= "000";
if I(7) = '1' then
A <= "111";
elsif I(6) = '1' then
A <= "110";
elsif I(5) = '1' then
A <= "101";
elsif I(4) = '1' then
A <= "100";
elsif I(3) = '1' then
A <= "011";
elsif I(2) = '1' then
A <= "010";
elsif I(1) = '1' then
A <= "001";
elsif I(0) = '1' then
A <= "000";
else
GS <= '0';
end if;
end process;
end v1;
8位相等比较器
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT688 is
port(Q, P : in std_logic_vector(7 downto 0);
GBAR : in std_logic; PEQ : out std_logic);
end HCT688;
architecture VER1 of HCT688 is
begin
PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1';
end VER1;
三人表决器（三种不同的描述方式）
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT688 is
port(Q, P : in std_logic_vector(7 downto 0);
GBAR : in std_logic; PEQ : out std_logic);
end HCT688;
architecture VER1 of HCT688 is
begin
PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1';
end VER1;
加法器描述
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT688 is
port(Q, P : in std_logic_vector(7 downto 0);
GBAR : in std_logic; PEQ : out std_logic);
end HCT688;
architecture VER1 of HCT688 is
begin
PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1';
end VER1;
8位总线收发器：74245 （注2）
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT688 is
port(Q, P : in std_logic_vector(7 downto 0);
GBAR : in std_logic; PEQ : out std_logic);
end HCT688;
architecture VER1 of HCT688 is
begin
PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1';
end VER1;
地址译码（for m68008）
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT688 is
port(Q, P : in std_logic_vector(7 downto 0);
GBAR : in std_logic; PEQ : out std_logic);
end HCT688;
architecture VER1 of HCT688 is
begin
PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1';
end VER1;
多路选择器（使用select语句）
-- 8-bit Identity Comparator
-- uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT688 is
port(Q, P : in std_logic_vector(7 downto 0);
GBAR : in std_logic; PEQ : out std_logic);
end HCT688;
architecture VER1 of HCT688 is
begin
PEQ <= '0' when ((To_X01(P) = To_X01(Q)) and (GBAR = '0')) else '1';
end VER1;
LED七段译码
--
------------------------------------------------------------------------------------
-- DESCRIPTION : BIN to seven segments converter
-- segment encoding
-- a
-- +---+
-- f | | b
-- +---+ <- g
-- e | | c
-- +---+
-- d
-- Enable (EN) active : high
-- Outputs (data_out) active : low
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity bin27seg is
port (
data_in : in std_logic_vector (3 downto 0);
EN : in std_logic;
data_out : out std_logic_vector (6 downto 0)
);
end entity;
architecture bin27seg_arch of bin27seg is
begin
process(data_in, EN)
begin
data_out <= (others => '1');
if EN='1' then
case data_in is
when "0000" => data_out <= "1000000"; -- 0
when "0001" => data_out <= "1111001"; -- 1
when "0010" => data_out <= "0100100"; -- 2
when "0011" => data_out <= "0110000"; -- 3
when "0100" => data_out <= "0011001"; -- 4
when "0101" => data_out <= "0010010"; -- 5
when "0110" => data_out <= "0000011"; -- 6
when "0111" => data_out <= "1111000"; -- 7
when "1000" => data_out <= "0000000"; -- 8
when "1001" => data_out <= "0011000"; -- 9
when "1010" => data_out <= "0001000"; -- A
when "1011" => data_out <= "0000011"; -- b
when "1100" => data_out <= "0100111"; -- c
when "1101" => data_out <= "0100001"; -- d
when "1110" => data_out <= "0000110"; -- E
when "1111" => data_out <= "0001110"; -- F
when others => NULL;
end case;
end if;
end process;
end architecture;
多路选择器（使用if－else语句）
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
x: out std_logic_vector(3 downto 0));
end mux;
architecture archmux of mux is
begin
mux4_1: process (a, b, c, d)
begin
if s = "00" then
x <= a;
elsif s = "01" then
x <= b;
elsif s = "10" then
x <= c;
else
x <= d;
end if;
end process mux4_1;
end archmux;
双2－4译码器：74139
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
x: out std_logic_vector(3 downto 0));
end mux;
architecture archmux of mux is
begin
mux4_1: process (a, b, c, d)
begin
if s = "00" then
x <= a;
elsif s = "01" then
x <= b;
elsif s = "10" then
x <= c;
else
x <= d;
end if;
end process mux4_1;
end archmux;
多路选择器（使用when－else语句）
-- Multiplexer 16-to-4 using if-then-elsif-else Statement
library ieee;
use ieee.std_logic_1164.all;
entity mux is port(
a, b, c, d: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
x: out std_logic_vector(3 downto 0));
end mux;
architecture archmux of mux is
begin
mux4_1: process (a, b, c, d)
begin
if s = "00" then
x <= a;
elsif s = "01" then
x <= b;
elsif s = "10" then
x <= c;
else
x <= d;
end if;
end process mux4_1;
end archmux;
二进制到BCD码转换
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Bin to Bcd converter
-- Input (data_in) width : 4
-- Output (data_out) width : 8
-- Enable (EN) active : high
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity bin2bcd is
port(
data_in : in std_logic_vector(3 downto 0);
EN : in std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity;
architecture bin2bcd of bin2bcd is
begin
process(data_in, EN)
variable data_in_TEMP : std_logic_vector(2 downto 0);
begin
data_in_TEMP := data_in(3 downto 1);
data_out <= (others => '0');
if EN='1' then
case data_in_TEMP is
when "000" => data_out(7 downto 1) <= "0000000";
when "001" => data_out(7 downto 1) <= "0000001";
when "010" => data_out(7 downto 1) <= "0000010";
when "011" => data_out(7 downto 1) <= "0000011";
when "100" => data_out(7 downto 1) <= "0000100";
when "101" => data_out(7 downto 1) <= "0001000";
when "110" => data_out(7 downto 1) <= "0001001";
when "111" => data_out(7 downto 1) <= "0001010";
when others => data_out <= (others => '0');
end case;
data_out(0) <= data_in(0);
end if;
end process;
end architecture;
多路选择器 （使用case语句）
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Bin to Bcd converter
-- Input (data_in) width : 4
-- Output (data_out) width : 8
-- Enable (EN) active : high
--
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity bin2bcd is
port(
data_in : in std_logic_vector(3 downto 0);
EN : in std_logic;
data_out : out std_logic_vector(7 downto 0)
);
end entity;
architecture bin2bcd of bin2bcd is
begin
process(data_in, EN)
variable data_in_TEMP : std_logic_vector(2 downto 0);
begin
data_in_TEMP := data_in(3 downto 1);
data_out <= (others => '0');
if EN='1' then
case data_in_TEMP is
when "000" => data_out(7 downto 1) <= "0000000";
when "001" => data_out(7 downto 1) <= "0000001";
when "010" => data_out(7 downto 1) <= "0000010";
when "011" => data_out(7 downto 1) <= "0000011";
when "100" => data_out(7 downto 1) <= "0000100";
when "101" => data_out(7 downto 1) <= "0001000";
when "110" => data_out(7 downto 1) <= "0001001";
when "111" => data_out(7 downto 1) <= "0001010";
when others => data_out <= (others => '0');
end case;
data_out(0) <= data_in(0);
end if;
end process;
end architecture;
二进制到格雷码转换
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Bin to gray converter
-- Input (DATA_IN) width : 4
-- Enable (EN) active : high
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity BIN2GARY is
port (
DATA_IN : in std_logic_vector (3 downto 0);
EN : in std_logic;
DATA_OUT : out std_logic_vector (3 downto 0)
);
end entity;
architecture bin2gary_arch of BIN2GARY is
begin
DATA_OUT(0) <= (DATA_IN(0) xor DATA_IN(1)) and EN;
DATA_OUT(1) <= (DATA_IN(1) xor DATA_IN(2)) and EN;
DATA_OUT(2) <= (DATA_IN(2) xor DATA_IN(3)) and EN;
DATA_OUT(3) <= DATA_IN(3) and EN;
end architecture;
双向总线（注2）
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Bin to gray converter
-- Input (DATA_IN) width : 4
-- Enable (EN) active : high
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity BIN2GARY is
port (
DATA_IN : in std_logic_vector (3 downto 0);
EN : in std_logic;
DATA_OUT : out std_logic_vector (3 downto 0)
);
end entity;
architecture bin2gary_arch of BIN2GARY is
begin
DATA_OUT(0) <= (DATA_IN(0) xor DATA_IN(1)) and EN;
DATA_OUT(1) <= (DATA_IN(1) xor DATA_IN(2)) and EN;
DATA_OUT(2) <= (DATA_IN(2) xor DATA_IN(3)) and EN;
DATA_OUT(3) <= DATA_IN(3) and EN;
end architecture;
汉明纠错吗译码器
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Bin to gray converter
-- Input (DATA_IN) width : 4
-- Enable (EN) active : high
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity BIN2GARY is
port (
DATA_IN : in std_logic_vector (3 downto 0);
EN : in std_logic;
DATA_OUT : out std_logic_vector (3 downto 0)
);
end entity;
architecture bin2gary_arch of BIN2GARY is
begin
DATA_OUT(0) <= (DATA_IN(0) xor DATA_IN(1)) and EN;
DATA_OUT(1) <= (DATA_IN(1) xor DATA_IN(2)) and EN;
DATA_OUT(2) <= (DATA_IN(2) xor DATA_IN(3)) and EN;
DATA_OUT(3) <= DATA_IN(3) and EN;
end architecture;
三态总线（注2）
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Bin to gray converter
-- Input (DATA_IN) width : 4
-- Enable (EN) active : high
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity BIN2GARY is
port (
DATA_IN : in std_logic_vector (3 downto 0);
EN : in std_logic;
DATA_OUT : out std_logic_vector (3 downto 0)
);
end entity;
architecture bin2gary_arch of BIN2GARY is
begin
DATA_OUT(0) <= (DATA_IN(0) xor DATA_IN(1)) and EN;
DATA_OUT(1) <= (DATA_IN(1) xor DATA_IN(2)) and EN;
DATA_OUT(2) <= (DATA_IN(2) xor DATA_IN(3)) and EN;
DATA_OUT(3) <= DATA_IN(3) and EN;
end architecture;
汉明纠错吗编码器
-- Hamming Encoder
-- A 4-bit Hamming Code encoder using concurrent assignments.
-- The output vector is connected to the individual parity bits using an aggregate assignment.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hamenc IS
PORT(datain : IN BIT_VECTOR(0 TO 3); --d0 d1 d2 d3
hamout : OUT BIT_VECTOR(0 TO 7)); --d0 d1 d2 d3 p0 p1 p2 p4
END hamenc;
ARCHITECTURE ver2 OF hamenc IS
SIGNAL p0, p1, p2, p4 : BIT; --check bits
BEGIN
--generate check bits
p0 <= (datain(0) XOR datain(1)) XOR datain(2);
p1 <= (datain(0) XOR datain(1)) XOR datain(3);
p2 <= (datain(0) XOR datain(2)) XOR datain(3);
p4 <= (datain(1) XOR datain(2)) XOR datain(3);
--connect up outputs
hamout(4 TO 7) <= (p0, p1, p2, p4);
hamout(0 TO 3) <= datain(0 TO 3);
END ver2;
解复用器
-- Hamming Encoder
-- A 4-bit Hamming Code encoder using concurrent assignments.
-- The output vector is connected to the individual parity bits using an aggregate assignment.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hamenc IS
PORT(datain : IN BIT_VECTOR(0 TO 3); --d0 d1 d2 d3
hamout : OUT BIT_VECTOR(0 TO 7)); --d0 d1 d2 d3 p0 p1 p2 p4
END hamenc;
ARCHITECTURE ver2 OF hamenc IS
SIGNAL p0, p1, p2, p4 : BIT; --check bits
BEGIN
--generate check bits
p0 <= (datain(0) XOR datain(1)) XOR datain(2);
p1 <= (datain(0) XOR datain(1)) XOR datain(3);
p2 <= (datain(0) XOR datain(2)) XOR datain(3);
p4 <= (datain(1) XOR datain(2)) XOR datain(3);
--connect up outputs
hamout(4 TO 7) <= (p0, p1, p2, p4);
hamout(0 TO 3) <= datain(0 TO 3);
END ver2;
