四D触发器：74175
-- Quad D-Type Flip-flop
-- This example shows how a conditional signal assignment statement could be used to describe sequential logic(it is more common to use a process).
-- The keyword 'unaffected' is equivalent to the 'null' statement in the sequential part of the language.
-- The model would work exactly the same without the clause 'else unaffected' attached to the end of the statement.
-- uses 1993 std VHDL
library IEEE;
use IEEE.Std_logic_1164.all;
entity HCT175 is
port(D : in std_logic_vector(3 downto 0);
Q : out std_logic_vector(3 downto 0);
CLRBAR, CLK : in std_logic);
end HCT175;
architecture VER1 of HCT175 is
begin
Q <= (others => '0') when (CLRBAR = '0')
else D when rising_edge(CLK)
else unaffected;
end VER1;
用状态机实现的计数器
-- MAX+plus II VHDL Example
-- State Machine
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY statmach IS
PORT(
clk : IN BIT;
input : IN BIT;
reset : IN BIT;
output : OUT BIT);
END statmach;
ARCHITECTURE a OF statmach IS
TYPE STATE_TYPE IS (s0, s1);
SIGNAL state : STATE_TYPE;
BEGIN
PROCESS (clk)
BEGIN
IF reset = '1' THEN
state <= s0;
ELSIF (clk'EVENT AND clk = '1') THEN
CASE state IS
WHEN s0=>
state <= s1;
WHEN s1=>
IF input = '1' THEN
state <= s0;
ELSE
state <= s1;
END IF;
END CASE;
END IF;
END PROCESS;
output <= '1' WHEN state = s1 ELSE '0';
END a;
简单的锁存器
-- Latch Inference
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END latchinf;
ARCHITECTURE maxpld OF latchinf IS
BEGIN
latch : PROCESS (enable, data)
BEGIN
IF (enable = '1') THEN
q <= data;
END IF;
END PROCESS latch;
END maxpld;
各种功能的计数器 -- MAX+plus II VHDL Example
-- Efficient Counter Inference
-- Copyright (c) 1994 Altera Corporation
Library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
ENTITY counters IS
PORT
(
d : IN INTEGER RANGE 0 TO 255;
clk : IN BIT;
clear : IN BIT;
ld : IN BIT;
enable : IN BIT;
up_down : IN BIT;
qa : OUT INTEGER RANGE 0 TO 255;
qb : OUT INTEGER RANGE 0 TO 255;
qc : OUT INTEGER RANGE 0 TO 255;
qd : OUT INTEGER RANGE 0 TO 255;
qe : OUT INTEGER RANGE 0 TO 255;
qf : OUT INTEGER RANGE 0 TO 255;
qg : OUT INTEGER RANGE 0 TO 255;
qh : OUT INTEGER RANGE 0 TO 255;
qi : OUT INTEGER RANGE 0 TO 255;
qj : OUT INTEGER RANGE 0 TO 255;
qk : OUT INTEGER RANGE 0 TO 255;
ql : OUT INTEGER RANGE 0 TO 255;
qm : OUT INTEGER RANGE 0 TO 255;
qn : OUT INTEGER RANGE 0 TO 255
);
END counters;
ARCHITECTURE a OF counters IS
BEGIN
-- An enable counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF enable = '1' THEN
cnt := cnt + 1;
END IF;
END IF;
qa <= cnt;
END PROCESS;
-- A synchronous load counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + 1;
END IF;
END IF;
qb <= cnt;
END PROCESS;
-- A synchronous clear counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt := 0;
ELSE
cnt := cnt + 1;
END IF;
END IF;
qc <= cnt;
END PROCESS;
-- An up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
cnt := cnt + direction;
END IF;
qd <= cnt;
END PROCESS;
-- A synchronous load enable counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt := d;
ELSE
IF enable = '1' THEN
cnt := cnt + 1;
END IF;
END IF;
END IF;
qe <= cnt;
END PROCESS;
-- An enable up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF enable = '1' THEN
cnt := cnt + direction;
END IF;
END IF;
qf <= cnt;
END PROCESS;
-- A synchronous clear enable counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt := 0;
ELSE
IF enable = '1' THEN
cnt := cnt + 1;
END IF;
END IF;
END IF;
qg <= cnt;
END PROCESS;
-- A synchronous load clear counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt := 0;
ELSE
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + 1;
END IF;
END IF;
END IF;
qh <= cnt;
END PROCESS;
-- A synchronous load up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt := d;
ELSE
cnt := cnt + direction;
END IF;
END IF;
qi <= cnt;
END PROCESS;
-- A synchronous load enable up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF ld = '0' THEN
cnt := d;
ELSE
IF enable = '1' THEN
cnt := cnt + direction;
END IF;
END IF;
END IF;
qj <= cnt;
END PROCESS;
-- A synchronous clear load enable counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt := 0;
ELSE
IF ld = '0' THEN
cnt := d;
ELSE
IF enable = '1' THEN
cnt := cnt + 1;
END IF;
END IF;
END IF;
END IF;
qk <= cnt;
END PROCESS;
-- A synchronous clear up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt := 0;
ELSE
cnt := cnt + direction;
END IF;
END IF;
ql <= cnt;
END PROCESS;
-- A synchronous clear enable up/down counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
VARIABLE direction : INTEGER;
BEGIN
IF (up_down = '1') THEN
direction := 1;
ELSE
direction := -1;
END IF;
IF (clk'EVENT AND clk = '1') THEN
IF clear = '0' THEN
cnt := 0;
ELSE
IF enable = '1' THEN
cnt := cnt + direction;
END IF;
END IF;
END IF;
qm <= cnt;
END PROCESS;
-- A modulus 200 up counter
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 255;
CONSTANT modulus : INTEGER := 200;
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF cnt = modulus THEN
cnt := 0;
ELSE
cnt := cnt + 1;
END IF;
END IF;
qn <= cnt;
END PROCESS;
END a;
简单的12位寄存器
-- User-Defined Macrofunction
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reg12 IS
PORT(
d : IN BIT_VECTOR(11 DOWNTO 0);
clk : IN BIT;
q : OUT BIT_VECTOR(11 DOWNTO 0));
END reg12;
ARCHITECTURE a OF reg12 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL clk = '1';
q <= d;
END PROCESS;
END a;
通用寄存器
-- Universal Register
-- This design is a universal register which can be used as a straightforward storage register, a bi-directional shift register, an up counter and a down counter.
-- The register can be loaded from a set of parallel data inputs and the mode is controlled by a 3-bit input.
-- The 'termcnt' (terminal count) output goes high when the register contains zero.
LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;
ENTITY unicntr IS
GENERIC(n : Positive := 8); --size of counter/shifter
PORT(clock, serinl, serinr : IN Std_logic; --serial inputs
mode : IN Std_logic_vector(2 DOWNTO 0); --mode control
datain : IN Std_logic_vector((n-1) DOWNTO 0); --parallel inputs
dataout : OUT Std_logic_vector((n-1) DOWNTO 0); --parallel outputs
termcnt : OUT Std_logic); --terminal count output
END unicntr;
ARCHITECTURE v1 OF unicntr IS
SIGNAL int_reg : Std_logic_vector((n-1) DOWNTO 0);
BEGIN
main_proc : PROCESS
BEGIN
WAIT UNTIL rising_edge(clock);
CASE mode IS
--reset
WHEN "000" => int_reg <= (OTHERS => '0');
--parallel load
WHEN "001" => int_reg <= datain;
--count up
WHEN "010" => int_reg <= int_reg + 1;
--count down
WHEN "011" => int_reg <= int_reg - 1;
--shift left
WHEN "100" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl;
--shift right
WHEN "101" => int_reg <= serinr & int_reg((n-1) DOWNTO 1);
--do nothing
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
det_zero : PROCESS(int_reg) --detects when count is 0
BEGIN
termcnt <= '1';
FOR i IN int_reg'Range LOOP
IF int_reg(i) = '1' THEN
termcnt <= '0';
EXIT;
END IF;
END LOOP;
END PROCESS;
--connect internal register to dataout port
dataout <= int_reg;
END v1;
带load、clr等功能的寄存器
-- Register Inference
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY reginf IS
PORT
(
d, clk, clr, pre, load, data : IN BIT;
q1, q2, q3, q4, q5, q6, q7 : OUT BIT
);
END reginf;
ARCHITECTURE maxpld OF reginf IS
BEGIN
-- Register with active-high Clock
PROCESS
BEGIN
WAIT UNTIL clk = '1';
q1 <= d;
END PROCESS;
-- Register with active-low Clock
PROCESS
BEGIN
WAIT UNTIL clk = '0';
q2 <= d;
END PROCESS;
-- Register with active-high Clock & asynchronous Clear
PROCESS (clk, clr)
BEGIN
IF clr = '1' THEN
q3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
q3 <= d;
END IF;
END PROCESS;
-- Register with active-low Clock & asynchronous Clear
PROCESS (clk, clr)
BEGIN
IF clr = '0' THEN
q4 <= '0';
ELSIF clk'EVENT AND clk = '0' THEN
q4 <= d;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous Preset
PROCESS (clk, pre)
BEGIN
IF pre = '1' THEN
q5 <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
q5 <= d;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous load
PROCESS (clk, load, data)
BEGIN
IF load = '1' THEN
q6 <= data;
ELSIF clk'EVENT AND clk = '1' THEN
q6 <= d;
END IF;
END PROCESS;
-- Register with active-high Clock & asynchronous Clear & Preset
PROCESS (clk, clr, pre)
BEGIN
IF clr = '1' THEN
q7 <= '0';
ELSIF pre = '1' THEN
q7 <= '1';
ELSIF clk'EVENT AND clk = '1' THEN
q7 <= d;
END IF;
END PROCESS;
END maxpld;
带三态输出的8位D寄存器：74374（注2）
-- Octal D-Type Register with 3-State Outputs
-- Simple model of an Octal D-type register with three-state outputs using two concurrent statements.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ttl374 IS
PORT(clock, oebar : IN std_logic;
data : IN std_logic_vector(7 DOWNTO 0);
qout : OUT std_logic_vector(7 DOWNTO 0));
END ENTITY ttl374;
ARCHITECTURE using_1164 OF ttl374 IS
--internal flip-flop outputs
SIGNAL qint : std_logic_vector(7 DOWNTO 0);
BEGIN
qint <= data WHEN rising_edge(clock); --d-type flip flops
qout <= qint WHEN oebar = '0' ELSE "ZZZZZZZZ"; --three-state buffers
END ARCHITECTURE using_1164;
移位寄存器：74164 -- TTL164 Shift Register
library IEEE;
use IEEE.Std_logic_1164.all;
ENTITY dev164 IS
PORT(a, b, nclr, clock : IN BIT;
q : BUFFER BIT_VECTOR(0 TO 7));
END dev164;
ARCHITECTURE version1 OF dev164 IS
BEGIN
PROCESS(a,b,nclr,clock)
BEGIN
IF nclr = '0' THEN
q <= "00000000";
ELSE
IF clock'EVENT AND clock = '1'
THEN
FOR i IN q'RANGE LOOP
IF i = 0 THEN q(i) <= (a AND b);
ELSE
q(i) <= q(i-1);
END IF;
END LOOP;
END IF;
END IF;
END PROCESS;
END version1;
8位数据锁存器
--
--
------------------------------------------------------------------------------------
-- DESCRIPTION : Flip-flop D type
-- Width: 8
-- Clock active: high
-- Synchronous clear active: high
-- Synchronous set active: high
-- Clock enable active: high
-- Load active: high
------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ffd is
port (
CLR : in std_logic;
SET : in std_logic;
CE : in std_logic;
LOAD : in std_logic;
CLK : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : out std_logic_vector (7 downto 0)
);
end entity;
architecture ffd_arch of ffd is
signal TEMP_DATA_OUT: std_logic_vector (7 downto 0);
begin
process (CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
if CLR = '1' then
TEMP_DATA_OUT <= (others => '0');
elsif SET = '1' then
TEMP_DATA_OUT <= (others => '1');
elsif LOAD = '1' then
TEMP_DATA_OUT <= DATA_IN;
end if;
end if;
end if;
end process;
DATA_OUT <= TEMP_DATA_OUT;
end architecture;
移位寄存器
--
--
---------------------------------------------------------------------------------------
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
-- Shift direction: right/left (right active high)
--
-- CLK active : high
-- CLR active : high
-- CLR type : synchronous
-- SET active : high
-- SET type : synchronous
-- LOAD active : high
-- CE active : high
-- SERIAL input : SI
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity shft_reg is
port (
DIR : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
SET : in std_logic;
CE : in std_logic;
LOAD : in std_logic;
SI : in std_logic;
DATA : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(3 downto 0)
);
end entity;
architecture shft_reg_arch of shft_reg is
signal TEMP_data_out : std_logic_vector(3 downto 0);
begin
process(CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
if CLR = '1' then
TEMP_data_out <= "0000";
elsif SET = '1' then
TEMP_data_out <= "1111";
elsif LOAD = '1' then
TEMP_data_out <= DATA;
else
if DIR = '1' then
TEMP_data_out <= SI & TEMP_data_out(3 downto 1);
else
TEMP_data_out <= TEMP_data_out(2 downto 0) & SI;
end if;
end if;
end if;
end if;
end process;
data_out <= TEMP_data_out;
end architecture;
